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1/13 march 1999 m14c16 M14C04 memory card ic 16/4 kbit serial i2c bus eeprom n two wire i 2 c serial interface supports 400 khz protocol n single supply voltage (2.5 v to 5.5 v) n hardware write control n byte and page write (up to 16 bytes) n byte, random and sequential read modes n self-timed programming cycle n automatic address incrementing n enhanced esd/latch-up behaviour n 1 million erase/write cycles (minimum) n 40 year data retention (minimum) n 5 ms programming time (typical) description each device is an electrically erasable program- mable memory (eeprom) fabricated with stmi- croelectronicss high endurance, single polysilicon, cmos technology. this guarantees an endurance typically well above one million erase/write cycles, with a data retention of 40 years. the memory operates with a power sup- ply as low as 2.5 v. the m14c16 and M14C04 are each available in wafer form (either sawn or unsawn) and in micro- module form (on film). each memory is compatible with the i 2 c memory standard. this is a two wire serial interface that figure 1. logic diagram ai02217 sda v cc m14xxx wc scl gnd table 1. signal names sda serial data/address input/ output scl serial clock wc write control v cc supply voltage gnd ground 2 2 2 2 micromodule (d20) wafer
m14c16, M14C04 2/13 uses a bi-directional data bus and serial clock. the memory carries a built-in 7-bit unique device type identifier code (1010xxx, for the m14c16, and 101000x, for the M14C04, as shown in table 3) in accordance with the i 2 c bus definition. only one memory can be attached to each i 2 c bus. the memory behaves as a slave device in the i 2 c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiated by a start condition, generated by the bus master. the start condition is followed by the device select code which is composed of a stream of 7 bits (1010xxx, for the m14c16, and 101000x, for the M14C04, as shown in table 3), plus one read/write bit (r/w ) and is terminated by an acknowledge bit. when writing data to the memory, the memory in- serts an acknowledge bit during the 9 th bit time, following the bus masters 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and af- ter a noack for read. power on reset: v cc lock-out write protect in order to prevent data corruption and inadvertent write operations during power up, a power on re- set (por) circuit is included. the internal reset is held active until the v cc voltage has reached the por threshold value, and all operations are dis- abled C the device will not respond to any com- mand. in the same way, when v cc drops from the operating voltage, below the por threshold value, all operations are disabled and the device will not respond to any command. a stable and valid v cc must be applied before applying any logic signal. signal description serial clock (scl) the scl input pin is used to synchronize all data in and out of the memory. a pull up resistor can be connected from the scl line to v cc . (figure 3 in- dicates how the value of the pull-up resistor can be calculated). serial data (sda) the sda pin is bi-directional, and is used to trans- fer data in or out of the memory. it is an open drain output that may be wire-ored with other open drain or open collector signals on the bus. a pull up resistor must be connected from the sda bus to v cc . (figure 3 indicates how the value of the pull-up resistor can be calculated). write control (wc ) the hardware write control contact (wc ) is useful for protecting the entire contents of the memory from inadvertent erase/write. the write control signal is used to enable (wc =v il ) or disable figure 2. d20 contact connections ai02168 v cc gnd scl sda wc table 2. absolute maximum ratings 1 note: 1. except for the rating operating temperature range, stresses above those listed in the table absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and operation of the device at these or any other conditio ns above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect device reliability. refer also to the st sure program and other relevant quality document s. 2. mil-std-883c, 3015.7 (100 pf, 1500 w ) 3. eiaj ic-121 (condition c) (200 pf, 0 w ) symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature wafer form module form -65 to 150 -40 to 120 c v io input or output range -0.6 to 6.5 v v cc supply voltage -0.3 to 6.5 v v esd electrostatic discharge voltage (human body model) 2 4000 v electrostatic discharge voltage (machine model) 3 400 v
3/13 m14c16, M14C04 (wc =v ih ) write instructions to the entire memory area. when unconnected, the wc input is internal- ly read as v il and write operations are allowed. when wc =1, device select and address bytes are acknowledged, data bytes are not acknowl- edged. please see the application note an404 for a more detailed description of the write control feature. device operation the memory device supports the i 2 c protocol, as summarized in figure 4. any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiv- er. the device that controls the data transfer is known as the master, and the other as the slave. a data transfer can only be initiated by the master, which will also provide the serial clock for synchro- nization. the memory device is always a slave de- vice in all communication. start condition start is identified by a high to low transition of the sda line while the clock, scl, is stable in the high state. a start condition must precede any data transfer command. the memory device con- tinuously monitors (except during a programming cycle) the sda and scl lines for a start condi- tion, and will not respond unless one is given. stop condition stop is identified by a low to high transition of the sda line while the clock scl is stable in the high state. a stop condition terminates communica- tion between the memory device and the bus mas- ter. a stop condition at the end of a read command, after (and only after) a noack, forces the memory device into its standby state. a stop condition at the end of a write command triggers the internal eeprom write cycle. acknowledge bit (ack) an acknowledge signal is used to indicate a suc- cessful data transfer. the bus transmitter, either master or slave, will release the sda bus after sending 8 bits of data. during the 9 th clock pulse period the receiver pulls the sda bus low to ac- knowledge the receipt of the 8 data bits. data input during data input, the memory device samples the sda bus signal on the rising edge of the clock, scl. for correct device operation, the sda signal must be stable during the clock low-to-high transi- tion, and the data must change only when the scl line is low. memory addressing to start communication between the bus master and the slave memory, the master must initiate a start condition. following this, the master sends 8 bits to the sda bus line (with the most significant bit first). these bits represent the device select code (7 bits) and a rw bit. the seven most significant bits of the device se- lect code are the device type identifier, according to the i 2 c bus definition. for the memory device, the seven bits are fixed as shown in table 3. the 8 th bit is the read or write bit (rw ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the cor- responding memory gives an acknowledgment on the sda bus during the 9 th bit time. if the memory does not match the device select code, it will de- select itself from the bus, and go into stand-by mode. figure 3. maximum r l value versus bus capacitance (c bus ) for an i 2 c bus ai01665 v cc c bus sda r l master r l scl c bus 100 0 4 8 12 16 20 c bus (pf) maximum rp value (k w ) 10 1000 fc = 400khz fc = 100khz
m14c16, M14C04 4/13 write operations following a start condition the master sends a device select code with the rw bit set to 0, as shown in table 4. the memory acknowledges it and waits for a byte address, which provides ac- cess to the memory area. after receipt of the ad- dress, the memory again responds with an acknowledge and waits for the data byte. writing in the memory may be inhibited if input pin wc is taken high. any write command with wc =1 (during a period of time from the start condition until the end of the address) will not modify the memory content and will not be acknowledged on data bytes, as shown in figure 5. figure 4. i 2 c bus protocol scl sda scl sda sda start condition sda input sda change ai00792 stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition table 3. device select code 1 note: 1. a10, a9 and a8 correspond to the most significant bits of the memory array address word. device code chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 m14c16 select 1010a10a9a8rw M14C04 select 101000a8rw
5/13 m14c16, M14C04 figure 5. write mode sequences with wc =1 stop start byte write dev sel byte addr data in wc start page write dev sel byte addr data in 1 data in 2 wc data in 3 ai02803b page write (cont'd) wc (cont'd) stop data in n ack ack no ack r/w ack ack no ack no ack r/w no ack no ack byte write in the byte write mode, after the device select code and the address, the master sends one data byte. if the addressed location is write protected by the wc pin, the memory replies with a noack, and the location is not modified. if, instead, the wc pin has been held at 0, as shown in figure 6, the memory replies with an ack. the master termi- nates the transfer by generating a stop condi- tion. page write the page write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same row in the memory: that is the most significant memory address bits (b10-b4 for the m14c16 and b8-b4 for the M14C04) are the same. the master sends from one up to 16 bytes of data, each of which is ac- knowledged by the memory if the wc pin is low. if the wc pin is high, each data byte is followed by a noack and the location is not modified. after each byte is transferred, the internal byte address coun- ter (the four least significant bits only) is incre- mented. the transfer is terminated by the master generating a stop condition. care must be taken to avoid address counter roll-over which could re- sult in data being overwritten. note that, for any byte or page write mode, the generation by the master of the stop condition starts the internal memory program cycle. this stop condition trig- gers an internal memory program cycle only if the stop condition is internally decoded immediately after the ack bit; any stop condition decoded out of this "10 th bit" time slot will not trigger the in- ternal programming cycle. all inputs are disabled until the completion of this cycle and the memory will not respond to any request. minimizing system delays by polling on ack during the internal write cycle, the memory discon- nects itself from the bus, and copies the data from its internal latches to the memory cells. the maxi- mum write time (t w ) is indicated in table 5, but the
m14c16, M14C04 6/13 figure 6. write mode sequences with wc =0 stop start byte write dev sel byte addr data in wc start page write dev sel byte addr data in 1 data in 2 wc data in 3 ai02804 page write (cont'd) wc (cont'd) stop data in n ack r/w ack ack ack ack ack ack r/w ack ack table 4. operating modes note: 1. x = v ih or v il . mode rw bit wc 1 bytes initial sequence current address read 1 x 1 start, device select, rw = 1 random address read 0 x 1 start, device select, rw = 0, address 1 x restart, device select, rw = 1 sequential read 1 x 3 1 similar to current or random mode byte write 0 v il 1 start, device select, rw = 0 page write 0 v il 16 start, device select, rw = 0 typical time is shorter. to make use of this, an ack polling sequence can be used by the master. the sequence, as shown in figure 7, is as follows: C initial condition: a write is in progress. C step 1: the master issues a start condition followed by a device select byte (first byte of the new instruction). C step 2: if the memory is busy with the internal write cycle, no ack will be returned and the master goes back to step 1. if the memory has terminated the internal write cycle, it responds
7/13 m14c16, M14C04 random address read a dummy write is performed to load the address into the address counter, as shown in figure 8. this is followed by another start condition from the master and the device select is repeated with the rw bit set to 1. the memory acknowledges this, and outputs the byte addressed. the master must not acknowledge the byte output, and termi- nates the transfer with a stop condition. sequential read this mode can be initiated with either a current address read or a random address read. how- ever, in this case the master does acknowledge the data byte output, and the memory continues to output the next byte in sequence. to terminate the stream of bytes, the master must not acknowledge the last byte output, and must generate a stop condition. the output data comes from consecu- tive addresses, with the internal address counter automatically incremented after each byte output. with an ack, indicating that the memory is ready to receive the second part of the next in- struction (the first byte of this instruction having been sent during step 1). read operations read operations are independent of the state of the wc pin. on delivery, the memory content is set at all 1s (ffh). current address read the memory has an internal address counter. each time a byte is read, this counter is increment- ed. for the current address read mode, following a start condition, the master sends a device se- lect with the rw bit set to 1. the memory ac- knowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the master must not acknowl- edge the byte output, and terminates the transfer with a stop condition, as shown in figure 8. figure 7. write cycle polling flowchart using ack write cycle in progress ai02165 next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop proceed write operation proceed random address read operation send byte address first byte of instruction with rw = 0 already decoded by m14xxx
m14c16, M14C04 8/13 after the last memory address, the address counter will roll-over and the memory will contin- ue to output data from the start of the memory block. acknowledge in read mode in all read modes the memory waits for an ac- knowledgment during the 9 th bit time. if the master does not pull the sda line low during this time, the memory terminates the data transfer and switches to its standby state. figure 8. read mode sequences note: 1. the seven most significant bits of the device select bytes of a random read (in the 1 st and 3 rd bytes) must be identical. start dev sel * byte addr start dev sel data out 1 ai01942 data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr sequential random read start dev sel * data out 1 stop ack r/w no ack ack r/w ack ack r/w ack ack ack no ack r/w no ack ack ack r/w ack ack r/w ack no ack
9/13 m14c16, M14C04 table 5. ac characteristics (t a = 0 to 70 c; v cc = 2.5 v to 5.5 v) note: 1. for a restart condition, or following a write cycle. 2. sampled only, not 100% tested table 6. dc characteristics (t a = 0 to 70 c; v cc = 2.5 v to 5.5 v) symbol alt. parameter fast i 2 c 400 khz i 2 c 100 khz unit min max min max t ch1ch2 2 t r clock rise time 300 1000 ns t cl1cl2 2 t f clock fall time 300 300 ns t dh1dh2 2 t r sda rise time 20 300 20 1000 ns t dl1dl2 2 t f sda fall time 20 300 20 300 ns t chdx 1 t su:sta clock high to input transition 600 4700 ns t chcl t high clock pulse width high 600 4000 ns t dlcl t hd:sta input low to clock low (start) 600 4000 ns t cldx t hd:dat clock low to input transition 0 0 s t clch t low clock pulse width low 1.3 4.7 s t dxcx t su:dat input transition to clock transition 100 250 ns t chdh t su:sto clock high to input high (stop) 600 4000 ns t dhdl t buf input high to input low (bus free) 1.3 4.7 s t clqv t aa clock low to data out valid 1000 3500 ns t clqx t dh data out hold time after clock low 200 200 ns f c f scl clock frequency 400 100 khz t w t wr write time 10 10 ms symbol parameter test condition min. max. unit i li input leakage current 0v v in v cc 2 a i lo output leakage current 0v v out v cc, sda in hi-z 2 a i cc supply current v cc =5v, f c =400khz (rise/fall time < 30ns) 2ma v cc =2.5v, f c =400khz (rise/fall time < 30ns) 1ma i cc1 supply current (stand-by) v in = v ss or v cc , v cc = 5 v 20 a v in = v ss or v cc , v cc = 2.5 v 1 a v il input low voltage (scl, sda) - 0.3 0.3 v cc v v ih input high voltage (scl, sda) 0.7 v cc v cc + 1 v v il input low voltage (wc ) - 0.3 0.5 v v ih input high voltage (wc ) v cc - 0.5 v cc + 1 v v ol output low voltage i ol = 3 ma, v cc = 5 v 0.4 v i ol = 2.1 ma, v cc = 2.5 v 0.4 v
m14c16, M14C04 10/13 figure 9. ac waveforms scl sda in scl sda out scl sda in tchcl tdlcl tchdx start condition tclch tdxcx tcldx sda input sda change tchdh tdhdl stop & bus free data valid tclqv tclqx data output tchdh stop condition tchdx start condition write cycle tw ai00795b figure 10. ac testing input output waveforms ai00825 0.8v cc 0.2v cc 0.7v cc 0.3v cc table 7. ac measurement conditions input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc input and output timing reference voltages 0.3v cc to 0.7v cc table 8. input parameters 1 (t a = 25 c, f = 400 khz) note: 1. sampled only, not 100% tested. symbol parameter test condition min. max. unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf t ns low pass filter input time constant (scl and sda) 100 400 ns
11/13 m14c16, M14C04 table 9. ordering information scheme example: M14C04 - w d20 memory capacity delivery form 16 16 kbit d20 module on super 35 mm film 04 4 kbit w2 unsawn wafer (275 m m 25 m m thickness) w4 unsawn wafer (180 m m 15 m m thickness) operating voltage w 2.5 v to 5.5 v s2x sawn wafer (275 m m 25 m m thickness) s4x sawn wafer (180 m m 15 m m thickness) where x indicates the sawing orientation, as follows (and as shown in figure 11) 1 gnd at top right 2 gnd at bottom right 3 gnd at bottom left 4 gnd at top left ordering information devices are shipped from the factory with the memory content set at all 1s (ffh). the notation used for the device number is as shown in table 9. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you. sawn wafers are scribed and mounted in a frame on adhesive tape. the orientation is defined by the position of the gnd pad on the die, viewed with active area of product visible, relative to the notch- es of the frame (as shown in figure 11). the orien- tation of the die with respect to the plastic frame notches is specified by the customer. one further concern, when specifying devices to be delivered in this form, is that wafers mounted on adhesive tape must be used within a limited pe- riod from the mounting date: C two months, if wafers are stored at 25c, 55% relative humidity C six months, if wafers are stored at 4c, 55% rel- ative humidity
m14c16, M14C04 12/13 figure 11. sawing orientation ai02171 1 orientation gnd gnd gnd gnd 234 view: wafer front side
13/13 m14c16, M14C04 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. ? 1998 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com

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